Sequential (158) Binding

https://johnchihau.blogspot.com/2026/08/blog-post.html?m=1

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Ref: https://johnchihau.blogspot.com/2026/08/blog-post.html?m=1

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John : Before we start,  you might read this. https://johnchihau.blogspot.com/2026/08/blog-post.html?m=1 .

Me: Ok.

John: See the 1st picture. After the multiplexer,  wifi1 enter the register called wifi1-register. The "control" of wifi1-register has "input and output" clock line.

Me: Ok.

John: But, the data of wifi1-register has only the output-clock line.

Me: Only output-Clock line?

John: Yes,

Me: In another words,  no matter the clock line is at up or down cycle,  input is available. 

John: Yes,.

Me: There's a problem.  The data of the address of wifi1 (0.0.0.0) will go "wrong" without an input clock line. An input Clock line is a Must.

John : You are wrong.  The address of wifi1 is fixed to 0000. In another words,  it is

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1) If the address of Wifi1 (0.0.0.0) is different at each clock cycle,  an input clock line is needed.

2) If the address of wifi1 (0.0.0.0) is same at each clock cycle, an input clock line isn't needed.

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Me: Ok. Now, I've got it.

John : Lastly,  I choose Wifi1,  it looks like the 2nd Picture.  

Me: There're 3 Circuits or 3 Chips in the 2nd Picture.

John: Yes, the signal of Wifi1 become the Clock line of Chip B. And Wifi1 become the Master of Chip B. In code, it looks like, 

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Int wifi = 0000;

Function Channel (wifi)

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